HOME / Blog / Unlocks 25μm Trace Widths in 1.6T OSFP-XD PCBs

How mSAP (Modified Semi-Additive Process) Unlocks 25μm Trace Widths in 1.6T OSFP-XD PCBs

JKRGLO R&D Engineer
07/14/2026
10:08 am

Opening Introduction

If you’re working on the next generation of AI networking hardware, you’ve likely hit the same wall I have: the physical density limits of traditional PCB manufacturing. With the 1.6T OSFP-XD form factor, the I/O density has become so aggressive that legacy subtractive etching can no longer keep up.

When you’re trying to route high-speed signals for 224G SerDes, you aren’t just fighting signal integrity—you’re fighting for every micron of routing space on the board. This is where mSAP (Modified Semi-Additive Process) is shifting from a “nice-to-have” to an absolute engineering requirement.

mSAP (Modified Semi-Additive Process)

In this post, I want to break down why mSAP is the secret sauce for achieving 25μm trace widths in 1.6T transceiver designs, and why switching to it might be the only way to avoid a total routing deadlock.

The "Subtractive" Deadlock: Why Traditional Etching Fails at 1.6T

Most of us grew up designing PCBs using a subtractive etching process. You start with a copper-clad laminate, apply a photoresist, and etch away the excess.

subtractive etching process

It’s reliable, it’s cheap, and it works great—until you push your trace widths below 50μm. The problem with subtractive etching is the “undercut.” Because the etchant attacks the copper both vertically and horizontally, you end up with a trapezoidal trace cross-section. At 25μm, that undercut isn’t just a rounding error; it’s a structural failure. It creates unpredictable impedance, massive signal reflections, and makes it impossible to maintain the tight tolerances required for 112 GHz operation.

For 1.6T OSFP-XD modules, which require high-density interconnects (HDI) to bridge the gap between the ASIC and the optical engines, traditional etching simply cannot deliver the geometry required for reliable signal integrity.

How mSAP Changes the Game

Unlike the subtractive process, mSAP is essentially “additive.” Here is the simplified flow of how it unlocks those 25μm geometries:

Thin Seed Layer: We start with a board coated in a very thin layer of electroless copper (the “seed” layer).
Patterning: Instead of etching copper away, we apply a photoresist to define the gaps where we don’t want traces.
Electroplating: We use electrolytic plating to build up the copper only in the open channels where the trace should be.
Flash Etch: Finally, we remove the photoresist and perform a quick, light etch to strip away the ultra-thin seed layer between the traces.

Because we are building the trace up rather than etching it down, the sidewalls of the copper are almost perfectly vertical (rectangular).

Why Rectangular Traces Matter for 1.6T

For a 224G SerDes signal, the electromagnetic field is extremely sensitive to the geometry of the conductor.

Impedance Control: A rectangular trace provides a consistent, predictable cross-section along the entire length of the channel.

Reduced Crosstalk: Because we can maintain a precise 25μm gap consistently, we can control the coupling between adjacent pairs much more tightly than with a traditional etched board.

Consistent Dielectric Load: You minimize the parasitic effects caused by varying trace shapes, which is the primary source of jitter in 1.6T links.

Practical Layout Challenges with mSAP

Transitioning to an mSAP-based fab isn’t just a drop-in replacement. If your design team is used to standard 2-mil (50μm) routing, you need to adjust your DFM (Design for Manufacturing) mindset.

Via Aspect Ratios: mSAP usually goes hand-in-hand with laser-drilled microvias. Keep your via aspect ratios (depth to diameter) conservative—aiming for 1:1 or less—to ensure reliable plating coverage in the via barrel.
Surface Finish Compatibility: Not all surface finishes play nice with 25μm lines. We’ve found that ENIG can sometimes cause brittle intermetallic compounds (IMCs) on such fine traces. Discuss with your fab whether ENEPIG or Immersion Silver is a better fit for your specific reliability requirements.
Registration Precision: When you are working at 25μm, the “registration” of the layers is everything. Ensure your manufacturer has the LDI (Laser Direct Imaging) capability to align the seed layer patterns to the microvias within a tolerance of $\pm 10\mu m$ .

Sourcing Considerations for 2026

If you’re shopping for a board house to handle your 1.6T OSFP-XD designs, don’t just ask if they “can do HDI.” Ask specifically for their mSAP line yield rates.

Many shops claim to handle 25μm, but their yield on a high-layer-count board is terrible because of contamination or inconsistent plating thickness. Look for shops that provide cross-sectional metallographic reports as part of their standard DFM feedback. If they can’t prove their trace profile is rectangular at the 25μm level, your signal integrity simulation results in HFSS or ADS aren’t going to match your lab results.

Final Thoughts

The shift to 25μm trace widths isn’t just about shrinking the board; it’s about enabling the sheer throughput required for 1.6T networking. While mSAP adds a layer of complexity and cost to the PCB manufacturing process, it’s the only way to get the signal integrity performance required for 224G PAM4.

If you’re currently stuck in a routing bottleneck for an OSFP-XD design, I highly recommend talking to your fab about migrating your critical signal layers to an mSAP process. It’s an investment, but it’s far cheaper than a re-spin caused by signal loss.

FAQ

Is mSAP more expensive than standard subtractive etching?

Yes, typically by 20% to 40% depending on the layer count and volume. However, when you factor in the reduced risk of signal integrity failures and the ability to fit more functionality into a smaller footprint, the total cost of ownership often comes out lower.

Can I use mSAP for my entire board stackup?

Usually, no. It’s best practice to use mSAP only for the critical signal layers (e.g., the high-speed SerDes traces) and use traditional subtractive processes for power and ground planes to keep costs under control. This is the hybrid approach most high-end OEMs use.

About US

Founded in 2012, JKRGLO strives to build a one-stop platform for the electronic industry chain. By integrating PCB manufacturing, component procurement and PCB assembly services, we enable digital PCBA processing. With increasing investment in innovation and digital systems, we have achieved rapid growth and emerged as a leading PCB and PCBA manufacturer in the industry, capable of rapidly producing high-reliability and cost-effective products.

About US