How mSAP (Modified Semi-Additive Process) Unlocks 25μm Trace Widths in 1.6T OSFP-XD PCBs
Opening Introduction
In this post, I want to break down why mSAP is the secret sauce for achieving 25μm trace widths in 1.6T transceiver designs, and why switching to it might be the only way to avoid a total routing deadlock.
The "Subtractive" Deadlock: Why Traditional Etching Fails at 1.6T
How mSAP Changes the Game
Thin Seed Layer: We start with a board coated in a very thin layer of electroless copper (the “seed” layer).
Patterning: Instead of etching copper away, we apply a photoresist to define the gaps where we don’t want traces.
Electroplating: We use electrolytic plating to build up the copper only in the open channels where the trace should be.
Flash Etch: Finally, we remove the photoresist and perform a quick, light etch to strip away the ultra-thin seed layer between the traces.
Because we are building the trace up rather than etching it down, the sidewalls of the copper are almost perfectly vertical (rectangular).
Why Rectangular Traces Matter for 1.6T
- Impedance Control: A rectangular trace provides a consistent, predictable cross-section along the entire length of the channel.
- Reduced Crosstalk: Because we can maintain a precise 25μm gap consistently, we can control the coupling between adjacent pairs much more tightly than with a traditional etched board.
- Consistent Dielectric Load: You minimize the parasitic effects caused by varying trace shapes, which is the primary source of jitter in 1.6T links.
Practical Layout Challenges with mSAP
Via Aspect Ratios: mSAP usually goes hand-in-hand with laser-drilled microvias. Keep your via aspect ratios (depth to diameter) conservative—aiming for 1:1 or less—to ensure reliable plating coverage in the via barrel.
Surface Finish Compatibility: Not all surface finishes play nice with 25μm lines. We’ve found that ENIG can sometimes cause brittle intermetallic compounds (IMCs) on such fine traces. Discuss with your fab whether ENEPIG or Immersion Silver is a better fit for your specific reliability requirements.
Registration Precision: When you are working at 25μm, the “registration” of the layers is everything. Ensure your manufacturer has the LDI (Laser Direct Imaging) capability to align the seed layer patterns to the microvias within a tolerance of $\pm 10\mu m$.
Sourcing Considerations for 2026
Final Thoughts
If you’re currently stuck in a routing bottleneck for an OSFP-XD design, I highly recommend talking to your fab about migrating your critical signal layers to an mSAP process. It’s an investment, but it’s far cheaper than a re-spin caused by signal loss.
FAQ
Is mSAP more expensive than standard subtractive etching?
Yes, typically by 20% to 40% depending on the layer count and volume. However, when you factor in the reduced risk of signal integrity failures and the ability to fit more functionality into a smaller footprint, the total cost of ownership often comes out lower.
Can I use mSAP for my entire board stackup?
Usually, no. It’s best practice to use mSAP only for the critical signal layers (e.g., the high-speed SerDes traces) and use traditional subtractive processes for power and ground planes to keep costs under control. This is the hybrid approach most high-end OEMs use.
